The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a multilayer interconnection structure and fabrication process thereof.
Conventionally, increase of operational speed of semiconductor devices has been attempted according to the so-called scaling law by miniaturizing the semiconductor device.
Meanwhile, such recent highly miniaturized semiconductor devices and integrated circuits generally use multilayer interconnection structure for interconnecting numerous semiconductor elements formed on the substrate. In such a multilayer interconnection structure, it should be noted that the total extension of the interconnection patterns has reached an enormous length and there arises a problem of serious signal delay caused by the multilayer interconnection structure.
Thus, investigations are being made for solving the foregoing problem of signal delay caused in a multilayer interconnection structure, by using an inorganic insulation film or organic insulation film having small specific dielectric constant for the insulation film that constitutes the interlayer insulation film of a multilayer interconnection structure in place of conventionally used insulation film of the SiO2 system, and further by using copper having a large atomic weight and low resistance for the interconnection pattern in place of conventionally used aluminum. In the case of using copper for the interconnection pattern, however, there arises a problem that patterning of the interconnection pattern by dry etching process, which has been used successfully in the conventional multilayer interconnection structure, is difficult. Because of this, copper interconnection patterns have been formed by way of so-called damascene process or dual damascene process.
However, there are still various problems to be solved in the art of damascene process when forming copper interconnection patterns such as large number of process steps. Further, there are remaining problems such as stress migrations, electromigrations, and the like.
In view of the foregoing situations, there are cases in current ultrafine semiconductor integrated circuits that use copper for the wiring patterns, to use a copper interconnection pattern formed by damascene process only for the lower layer part where the demand for suppressing the signal delay is stringent while continuously using aluminum multilayer interconnection structure in the upper layer part where the demand of suppressing signal delay is less stringent.
In the case of forming a multilayer interconnection structure having an aluminum interconnection pattern on a multilayer interconnection structure that uses a copper interconnection pattern, there is a need of connecting the lower level copper interconnection pattern and an upper level aluminum interconnection pattern electrically by way of a conductive plug. Conventionally, tungsten, capable of being formed by a CVD process and thus capable of filling a minute via-hole with excellent step coverage, has been used extensively for such a conductive plug.
FIG. 1 shows a connection structure 10 that connects a lower level copper interconnection pattern and an upper level aluminum interconnection pattern through a tungsten plug formed in an interlayer insulation film. It should be noted that the connection structure 10 of FIG. 1 is the one formed in the investigation made by the inventor of the present invention and constituting the foundation of the present invention.
Referring to FIG. 1, a wiring groove 11G having a side wall and a bottom surface covered with a barrier metal film 11A is formed in the interlayer insulation film 11 in the conventional connection structure 10, and the wiring groove 11G is filled with a copper interconnection pattern 11Cu formed by a damascene process or a dual damascene process. As a result of the CMP process associated with the damascene process, the interlayer insulation film 11 and the copper interconnection pattern 11Cu have the same top principal surface, and a next interlayer insulation film 12 is formed on such a top principal surface via a barrier film 12N, which may be formed of SiN, and the like.
In the interlayer insulation film 12, there is formed a via-hole 12V penetrating through the barrier film 12N so as to expose the copper interconnection pattern 11C, and the side wall surface and the bottom surface of the via-hole 12V are covered by a barrier metal film 12A, which in turn is formed by consecutively stacking a TaN film 12a and a Ta film 12b, and further a barrier metal film 12B of TiN formed on the barrier metal film 12A. In the via-hole 12V thus covered with the barrier metal films 12A and 12B, a tungsten plug 12W is formed so as to fill the space inside the via-hole 12V by a CVD process and a CMP process conducted after the CVD process.
Further, an aluminum interconnection pattern 13 formed of an aluminum base alloy such as aluminum or aluminum copper is formed on the interlayer insulation film 12, in which the tungsten plug 12W is thus formed, via an adhesion film 13A of Ti and a barrier metal film 13B of TiN.
In the illustrated example, another barrier metal film 13C of TiN is formed on the surface of the aluminum interconnection pattern 13 as usual.
Further, there has been a proposal of connecting the copper interconnection pattern of upper level and the copper interconnection pattern of lower level also by using such a tungsten plug.
FIGS. 2A–2E show the process of forming the connection structure of FIG. 1.
Referring to FIG. 2A, the SiN film 12N is deposited on the interlayer insulation film 11, in which the copper interconnection pattern 11Cu is embedded by a damascene process not illustrated, by conducting a plasma-enhanced CVD process. Next, in the step of FIG. 2B, the interlayer insulation film 12 is formed on the SiN film 12N by a plasma-enhanced CVD process etc. In the step of FIG. 2B, a via-hole 12V is formed further in the interlayer insulation film 12 through the SiN film 12N so as to expose the copper interconnection pattern 11Cu.
Next, in the step of FIG. 2C, a dry etching process is conducted to the copper interconnection pattern 11Cu exposed in the step of FIG. 2B by using high frequency plasma with a depth of about 15 nm such that the via-hole diameter is increased slightly at the upper part of the via-hole 12V, and the TaN film 12a and the Ta film 12b are deposited on the structure of FIG. 2B by a reaction sputtering process so as to include the via-hole 12V. With this, the barrier metal film 12A is formed. Further, in the step of FIG. 2C, the TiN film 12B is formed on the barrier metal film 12A as the next barrier metal film also by a reactive sputtering process.
In a typical example, the TaN film 12a and the Ta film 12b are formed to have the thicknesses of 20 nm and 30 nm, respectively, while the TiN film 12B is formed to have the thickness of 50 nm. In such a construction, the barrier metal films 12A and 12B form a TaN/Ta/TiN stacked structure. Alternatively, it is possible to form a TaN/Ta/TaN/Ta/TiN structure by repeatedly stacking the TaN film 12a and the Ta film 12b in the barrier metal film 12A. In this case, the TaN film may be formed to have the thickness of 10 nm and the Ta film may be formed to have the thickness of 15 nm.
Further, a tungsten film 12 is deposited in the step of FIG. 2D on the structure of FIG. 2C so as to fill the via-hole 12V by conducting by a CVD process while using WF6 as a gaseous source. By removing the tungsten film 12 and also the barrier metal films 12B and 12A consecutively from the interlayer insulation film 12 by a CMP process, the structure of FIG. 2E is obtained.
By forming the barrier metal films 13A and 13B and further the aluminum interconnection pattern 13 on the structure of FIG. 2E thus obtained, the structure shown in FIG. 1 is obtained.